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Figure 26 provides the AC test load.
Output
Z 0 = 50 Ω
R L = 50 Ω
V DDGE /2
Figure 26. AC Test Load
Figure 27 shows the MII receive AC timing diagram.
RX_CLK
RXD[3:0]
RX_DV
Valid Data
RX_ER
t MRDVKH
t MRDXKH
Figure 27. MII Receive AC Timing
2.6.10.4
RMII Transmit and Receive AC Timing Specifications
Table 43 provides the RMII transmit and receive AC timing specifications.
Table 43. RMII Transmit and Receive AC Timing Specifications
Parameter/Condition
REF_CLK duty cycle
REF_CLK to RMII data TXD[1–0], TX_EN delay
RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK
Symbol 1
t RMXH/ t RMX
t RMTKHDX
t RMRDVKH
t RMRDXKH
Min
35
2
4.0
2.0
Max
65
10
—
—
Unit
%
ns
ns
ns
Typical REF_CLK clock period (t RMX ) is 20 ns
Notes:
56
1.
2.
Typical REF_CLK clock period (t RMX ) is 20 ns
Program GCR4 as 0x00001405
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
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